19
?2007 Semtech Corp.
www.semtech.com
SC2463
POWER MANAGEMENT
Applications Information (Cont.)
3. Select ?/SPAN>
Z1
and ?/SPAN>
Z2
such that they are placed near ?/SPAN>
O
to dampen peaking; the loop gain has 20dB rate
to go across the 0dB line for obtaining a wide band-
width.
4. Cancel ?/SPAN>
ESR
with compensation pole ?/SPAN>
P1
(?/SPAN>
P1
= ?/SPAN>
ESR
).
5. Place a high frequency compensation pole ?/SPAN>
P2
at the
half switching frequency to get the maximum attenu-
ation of the switching ripple and the high frequency
noise with the adequate phase lag at ?/SPAN>
C
.
The compensated loop gain will be as given in Figure 8:
-20dB/dec
0dB
Gvd
T(s)
?/DIV>
z1
?/DIV>
z2
?/DIV>
o
?/DIV>
c
?/DIV>
p1
?/DIV>
ESR
?/DIV>
p2
Loop gain T(s)
Power stage
G
VD
(s)
-40dB/dec
-20dB/dec
0dB
Gvd
T(s)
?/DIV>
z1
?/DIV>
z2
?/DIV>
o
?/DIV>
c
?/DIV>
p1
?/DIV>
ESR
?/DIV>
p2
Loop gain T(s)
Power stage
G
VD
(s)
-40dB/dec
Figure 8. Asymptotic diagram of buck power stage and
its compensated loop gain
Dual Positive LDOs Controller
The SC2463 provides two positive adjustable linear regu-
lator controllers. The first positive linear regulator uses a
PNP transistor to regulate output voltage. This is set by
a voltage divider connected from the output to FB to
AGND. Referring to the front page Application Circuit,
select R10 in the 5K& to 20K& range. Calculate R9 with
the following equation:
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
1
5
.
0
V
R
R
OUT
10
9
The second positive linear regulator uses a NPN transis-
tor to regulate output voltage. This is set by a voltage
divider connected from the output to FB to AGND. Re-
ferring to the front page Application Circuit, select R18
in the 5K& to 20K& range. Calculate R14 with the
following equation:
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
1
5
.
0
V
R
R
OUT
18
14
The maximum voltage to drive an NPN transistor is AVCC
minus the voltage drop across the internal P-MOSFET
which is the product of On-Resistance and sourcing cur-
rent. The maximum driving voltage with 5mA sourcing
current is minimum AVCC (4.5V) minus 5mA times maxi-
mum On-Resistance 140&, i.e. 3.8V.
Layout Guidelines
Layout Guidelines
Layout Guidelines
Layout Guidelines
Layout Guidelines
In order to achieve optimal electrical, thermal and noise
performance for high frequency converters, attention
must be paid to the PCB layouts. The goal of layout opti-
mization is to place components properly and identify
the high di/dt loops to minimize them. The following guide-
lines should be used to ensure proper functions of the
converters:
1. A ground plane is recommended to minimize noises
and copper losses, and maximize heat dissipation.
2. Start the PCB layout by placing the power compo-
nents first. Arrange the power circuit to achieve a
clean power flow route. Put all the connections on
one side of the PCB with wide copper filled areas if
possible.
3. The PVCC and AVCC bypass capacitors should be
placed next to the PVCC, AVCC and PGND, AGND pins
respectively.
4. Separate the power ground from the signal ground.
In SC2463, the power ground PGND should be tied
to the source terminal of lower MOSFETs. The signal
ground AGND should be tied to the negative termi-
nal of the output capacitor.
5. The trace connecting the feedback resistors to the
output should be short, direct and far away from the
noise sources such as switching node and switching
components. Minimize the traces between DRXH/
DRXL and the gates of the MOSFETs to reduce their
impedance to drive the MOSFETs.
7. Minimize the loop including input capacitors, top/bot-
tom MOSFETs. This loop passes high di/dt current.
Make sure the trace width is wide enough to reduce
copper losses in this loop.
8. Maximize the trace width of the loop connecting the
inductor, bottom MOSFET and the output capacitors.
9. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC2463 by using a separate ground trace.
Then connect this pin to the ground of the output
capacitor as close as possible.
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